EDN

Speed with flexible design critical to embedded DRAM for SoCs

Steven Tomashot, Senior Technical Staff Member, IBM Microelectronics Division, Essex Junction, Vermont, Subramanian S. Iyer, Manager, System Scale Integration, IBM Microelectronics Division, Hopewell ...
Semiconductor Engineering

Identifying DRAM Failures Caused By Leakage Current And Parasitic Capacitance

Leakage current has been a leading cause of device failure in DRAM design, starting with the 20nm technology node. Problems with leakage current in DRAM design can lead to reliability issues, even ...
Electronic Design

Surrounding Gate Transistors May Improve DRAM

DRAM makes up the bulk of non-volatile memory in computer systems. Much has been done lately to mix non-volatile storage with DRAM. However, DRAM’s performance and capacity still win out when it comes ...
Nasdaq

Synopsys and TSMC Advance Analog Design Migration with Reference Flow Across Advanced TSMC Processes

AI-driven design solution enables circuit optimization, saving weeks of manual and iterative effort while increasing design quality. Interoperable process design kits for all advanced TSMC FinFET ...
EDN

Current Chip Design Flow is Flawed

As in any other engineering activity, the design of semiconductor chips (ICs) encompasses several separate, but often closely coupled, design activities. Today's system-on-a-chip (SoC) development ...