EDN

RTL synthesis can accelerate the entire implementation flow

You work in an environment where demanding design goals and aggressive project schedules go hand-in-hand with the push to get more complex products to market faster. And you have just finalized the ...
EDN

Exploring new design flows — RTL synthesis

Editor's Note: In Part 2 of this series,consultant and ASIC designer Tom Moxoncovered several trends in virtual silicon prototying design flows.In this installment of the series he'll show how to link ...
Semiconductor Engineering

Top Five Trends In RTL Signoff

The “shift left” of the development cycle is critical for the huge, complex chips used in such applications as AI and high-performance computing (HPC). Identifying design issues at the netlist stage ...
Semiconductor Engineering

High-Level Synthesis: It’s Still Hardware Design

Hardware design using HLS is no different than the typical ASIC/FPGA design flow with the exception that C++/SystemC is being used along with HLS to create the RTL instead of hand coding it. The ...
Electronic Design

Router, Signal-Integrity Tools Complete RTL-To-GDSII Flow

In one fell swoop, Synopsys Inc. of Mountain View, Calif., has completed its RTL-to-GDSII design tool flow with the introduction of two tools built into its Physical ...