EDN

Speed with flexible design critical to embedded DRAM for SoCs

Steven Tomashot, Senior Technical Staff Member, IBM Microelectronics Division, Essex Junction, Vermont, Subramanian S. Iyer, Manager, System Scale Integration, IBM Microelectronics Division, Hopewell ...
Semiconductor Engineering

Identifying DRAM Failures Caused By Leakage Current And Parasitic Capacitance

Leakage current has been a leading cause of device failure in DRAM design, starting with the 20nm technology node. Problems with leakage current in DRAM design can lead to reliability issues, even ...
Semiconductor Engineering

Improving DRAM Performance Using Dual Work-Function Metal Gate (DWMG) Structures

Dynamic Random Access Memory (DRAM) serves as the backbone of modern computing, enabling devices ranging from smartphones to high-performance servers. As the demand accelerates for higher density and ...
Nasdaq

Synopsys and TSMC Advance Analog Design Migration with Reference Flow Across Advanced TSMC Processes

AI-driven design solution enables circuit optimization, saving weeks of manual and iterative effort while increasing design quality. Interoperable process design kits for all advanced TSMC FinFET ...
EDN

A new platform for thermally stable DRAM peripheral transistors

Dynamic random-access memory (DRAM) chips contain many other transistors besides the access transistor to enable full operation of the DRAM memory. These peripheral transistors must meet stringent ...